A review on CMOS delay lines with a focus on the most frequently used techniques\nfor high-resolution delay step is presented. The primary types, specifications, delay\ncircuits, and operating principles are presented. The delay circuits reported in this\npaper are used for delaying digital inputs and clock signals. The most common analog\nand digitally-controlled delay elements topologies are presented, focusing on the main\ndelay-tuning strategies. IC variables, namely, process, supply voltage, temperature,\nand noise sources that affect delay resolution through timing jitter are discussed. The\ndesign specifications of these delay elements are also discussed and compared for the\ncommon delay line circuits. As a result, the main findings of this paper are highlighting\nand discussing the followings: the most efficient high-resolution delay line techniques,\nthe trade-off challenge found between CMOS delay lines designed using either analog\nor digitally-controlled delay elements, the trade-off challenge between delay resolution\nand delay range and the proposed solutions for this challenge, and how CMOS\ntechnology scaling can affect the performance of CMOS delay lines. Moreover, the current\ntrends and efforts used in order to generate output delayed signal with low jitter\nin the sub-picosecond range are presented.
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